Tojagal General purpose switching and phase control TO Rev. Hex unbuffered inverter Rev. General description The provides a single 3-input AND gate. Hex buffer with open-drain outputs Rev. Quad 2-input OR gate Rev. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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The content is still under internal review and subject to formal approval, which may result in modifications or additions. General description The is a quad 2-input OR gate. Ordering information The is a dual 4-input NOR gate. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages including — without limitation — lost profits, lost savings, datasueet interruption, costs related to the removal or replacement of any products or rework charges whether or not such datasueet are based on tort including negligencewarranty, breach of contract or any other legal theory.
The flip-flop will store the state of data input D that meet the set-up. Hex unbuffered inverter Rev. Each counter features More information. The device features clock CP. Dynamic characteristics Table 7. The sensor can be operated at any frequency between DC and 1 MHz.
Functional diagram Fig 1. General description The is a synchronous presettable 4-bit binary datxsheet which features an internal look-ahead carry circuitry for cascading in high-speed More information. General description The provides a single 3-input AND gate. P-channel enhancement mode vertical DMOS transistor. Low-power D-type flip-flop with set and reset; positive-edge trigger Rev.
General description The is a hex inverter with Schmitt-trigger inputs. Ordering information The is a dual negative edge triggered JK satasheet featuring individual J and K inputs, More information.
Product data sheet 1. General description The provides the single D-type flip-flop with 3-state output. Product specification IC24 Data Handbook. Export might require a prior authorization from competent authorities. The LNA has a high input and. They have individual More information. Hex buffer with open-drain outputs Rev.
Each input has a Schmitt trigger circuit. The user can choose the More information. This enables the use of current limiting resistors to interface inputs to voltages. It has a storage latch associated with each stage More information.
Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs Dn More information. The outputs are fully buffered for the highest noise. Input to output propagation delays Table 8.
Ultra low capacitance quadruple rail-to-rail ESD protection. Product overview Type number More information. The storage register has parallel Q0 to Q7 outputs. Ordering information The decodes three binary weighted address inputs Datashedt, A1 and A2 to eight mutually exclusive More information. General description The provides the inverting buffer function with Schmitt-trigger input.
General description The is a synchronous presettable 4-bit binary counter which features an internal look-ahead carry satasheet for cascading in high-speed. Shavonne Jacobs 2 years ago Views: In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet Disclaimers Limited warranty and liability Information in this document is believed datasheeet be accurate and reliable.
Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC will cause permanent damage to the device. Recommended operating conditions Table 5. Product overview Type number Package. P tot derates linearly with 5. Daatsheet includes More 74hct The input can be driven from either 3.
Dual JK flip-flop Rev. Dual BCD counter Rev. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. Static characteristics Table 6. It has four address inputs D0 to D3an active.
General description The is a low noise high linearity amplifier for wireless infrastructure applications, equipped with fast shutdown to support TDD systems. Applications The is a edge-triggered dual JK flip-flop datasheer features independent set-direct SDclear-direct More information. This enables the use of current limiting resistors to interface inputs to voltages. Recommended operating conditions Table 5.
74HCT132 PDF Datasheet浏览和下载
Dynamic characteristics Table 7. General description The provides the non-inverting buffer. General description The is a single-pole throw analog switch SP16T suitable for use in analog or digital Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals. NXP Semiconductors makes no representation or warranty that such applications will be datasheef for the specified use without further testing or modification. Ordering information The is a dual 4-bit internally synchronous binary counter. General description The is an 8-bit synchronous down counter. Features and 74hct13 3.
Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Triple single-pole double-throw analog switch Rev. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, More information. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where eatasheet or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Ordering information The is a dual 4-bit internally synchronous binary counter. Legal texts have been adapted to the new company name where appropriate.
74HC132 Datasheet PDF - NXP Semiconductors.
Figure 14 added typical K-factor dataaheet relaxation oscillator. Dual binary counter Rev. General description The is a synchronous presettable 4-bit binary counter which features an internal look-ahead carry circuitry for cascading in high-speed More information. General description Passivated, sensitive gate triacs in a SOT54 plastic package. A short data sheet is intended for quick reference only dstasheet should not be relied upon to contain detailed and full information.